CV

Senior Software Systems Engineer

PDF Solutions

GAN-based SEM ↔ Layout Translation System (Jan 2026 - Present)

• Built a GAN-based machine learning image-to-image translation system (U-Net + PatchGAN) for SEM ↔ layout simulation domain translation in semiconductor inspection.
• Designed multi-objective loss functions (adversarial + L1 + cycle consistency) to preserve geometric fidelity while improving visual realism.
• Deployed the model as a RESTful API (FastAPI) for scalable inference and integration into inspection and analysis workflows.
• Designed a closed-loop ML system with drift detection and human-in-the-loop feedback, enabling continuous improvement via automated fine-tuning and evaluation gating.

1D Registration Location Discovery – Geometry-based Pattern Search (Sep 2025 – Jan 2026)

• Designed a geometry-aware search system to identify robust registration locations from semiconductor layouts using edge-based spatial analysis.
• Built efficient candidate generation and filtering mechanisms with spatial indexing and rule-based isolation constraints for structured layout patterns.
• Developed scoring strategies to evaluate pattern quality and robustness under highly noisy conditions.
• Designed and integrated an end-to-end pipeline from layout parsing to candidate search and result generation, deployed on HPC (SGE clusters) for scalable large-scale layout processing.

Image-based Registration & Template Matching Pipeline (Apr 2025 – Sep 2025)

• Designed an end-to-end image-based pipeline for registration location selection in huge chip design layout(~mm^2), including layout rasterization, candidate sampling, template matching, and quality scoring.
• Applied computer vision techniques (template matching and correlation analysis) to identify robust patterns under noise, ambiguity, and repetitive structures.
• Developed data-driven quality metrics (e.g., peak ratio, feature coverage) for pattern ranking and selection.
• Improved pipeline efficiency by ~3×, leading to substantial reductions in compute cost and infrastructure usage, while enhancing code maintainability and debuggability by replacing legacy black-box EDA components with transparent, modular implementations.
• Built scalable and production-ready workflows, deployed across HPC (SGE) and AWS with debugging and validation pipelines for large-scale semiconductor inspection.

Automated 1D Registration Ranking & Selection System (May 2024 - Oct 2024)

• Designed an automated pipeline for registration candidate ranking and selection in semiconductor inspection workflows.
• Modeled the problem as a candidate scoring task using edge-based features (Sobel gradient, signal contrast) to evaluate registration quality.
• Implemented a multi-stage pipeline (generate → score → rank → select) to replace failed or low-quality locations with optimal alternatives.
• Improved registration accuracy from 98% to 99% across ~1M locations, reducing error cases by ~50% (~10K fewer failures).
• Enhanced system robustness by filtering false-pass and weak-signal candidates under noisy and repetitive conditions.

Data-Driven 2D Registration Tuning System (June 2023 - Dec 2023)

• Built a data-driven system for registration tuning and candidate filtering in semiconductor inspection workflows,resulting in 99% system registration pass rate for CPU and GPU chip defect detection
• Modeled the problem as a scoring and ranking task using 2D spatial features and 1D signal statistics to identify high-quality alignment locations under noise.
• Designed adaptive thresholding and failure-type classification (e.g., false pass, multi-peak ambiguity) to improve robustness and generalization.
• Reduced manual tuning effort by >90% (~20 min → <1 min) while improving consistency and interpretability through intermediate outputs.

Customer Collaboration & Technical Leadership

• Acted as a customer-facing engineer, delivering live demos of e-beam inspection systems to customers.
• Provided on-site and remote technical support, diagnosing complex registration and inspection issues in real production environments.
• Partnered with product managers and application engineers to translate customer requirements into scalable and testable technical solutions.
• Authored reproducible documentation and guided offshore teams in model deployment, debugging, and system validation.

Graduate Research Assistant

Vanderbilt University

Ph.D. research in optoelectronic characterization, signal processing, and data-driven analysis

• Performed optoelectronic characterization using scanning photocurrent microscopy (SPCM), generating spatially-resolved signal maps for device behavior and defect patterns.
• Analyzed photocurrent and electrical signals to characterize carrier transport, device variability, and pattern-level anomalies across spatial regions.
• Developed signal and image processing pipelines (MATLAB/Python) for noise reduction, feature extraction, and spatial pattern recognition.
• Explored data-driven approaches for pattern analysis and feature extraction from high-dimensional measurement data.

Ph.D.

Vanderbilt University

Electrical Engineering and Computer Science

B.Sc.

Huazhong University of Science and Technology

Materials Forming and Control Engineering

Hamilton Fellowship

Vanderbilt University

Fellowship awarded to support doctoral studies.